University of West Attica
Department of Informatics and Computer Engineering
Computer Systems Engineering
Code:
Semester:
Type:
Direction:
ICE-7101
7th
Compulsory for Direction
Hardware and Computer Systems
Course hours:
Instructors:
Links:
2 Lec – 2 T – 1 Lab
Alexandros Mpousdekis (ESPA)
Description
Instruction Set Architectures of RISC processors. Mips pipeline implementation – data hazards, control/branch hazards, dependencies, result forwarding, stall, delayed branch. Memory-hierarchy organization – cache memories. Instruction-level parallelism – superscalar processors, VLIW, out of order execution, register renaming, branch prediction.
I/O. Hardware interrupts. Modern processors. Clusters – interconnection networks.